1. Field of Invention
The invention relates generally to integrated circuits having repeated configurable logic and configurable interconnect structures provided therein. The invention relates more specifically to the problem of thoroughly and quickly testing large numbers and different types of interconnect resources such as those provided within an integrated circuit monolith that contains a programmable logic circuit such as a field programmable gate array (FPGA).
2. Description of Related Art
As the density of programmably-reconfigurable, digital logic circuitry within integrated circuits (IC""s) increases, and as the signal-processing speed of such logic also increases, the ability of all parts of the interconnect within the IC to correctly and consistently route all signals in timely and accurate fashion between spaced-apart logic sections (e.g., CLB""s or Configurable Logic Blocks) becomes more and more important to proper operation of the integrated circuit.
Individual ones of mass-produced, in-field re-programmable IC""s may have a number of localized defects within their interconnect resources such as: regional or spot short-circuits; broken-open lines; lines stuck-at a particular logic level; stuck-open signal routers; and stuck-closed signal routers. Any one or more of these and yet other circuit defects can interfere with proper device operation. Accordingly it is desirable to be able to test the interconnect resources of such mass-produced IC""s thoroughly, or as near thoroughly as practical, in order to provide a commensurate level of confidence (e.g., close to 100% test coverage) regarding the in-field operability of the interconnect. It is further desirable to be able to test the interconnect resources of such mass-produced IC""s in a time efficient manner and to minimize the use of expensive test equipment thereby allowing for economical verification of the hypothesis that all or a substantial portion of the IC""s resources are functioning as intended.
Testing of interconnect resources (hereafter, interconnect verification testing or xe2x80x98IVTxe2x80x99) at high speed and with thorough; or close-to-thorough coverage, is particularly difficult to achieve in cases where the interconnect is programmably re-configurable and the IVT is being conducted after the IC chips have been packaged in their respectively insulating, and pin-out limited carriers (e.g., ceramic IC packages). One reason for the difficulty is that each part of the configurable interconnect can have a large number of connection permutations, all of which may need to be tested during IVT in order to provide confidence that the configurable interconnect is fully operational. Another reason for the difficulty is that direct access to all internal nodes of the IC is usually no longer available after the IC has been encased in its package. Testers are limited to electrically coupling to the chip""s interior by way of the limited number of external pins or terminals that are provided by the package""s pinout.
Even before the above-described post-packaging phase, in a so-called, wafer-sort testing phase which occurs prior to packaging, the number of on-die, exposed nodes available to the testing equipment is limited by a number of factors including the number and types of probe fingers on the test equipment and the number of probe-able nodes (e.g., pads) provided on each IC die. While these constraints on testability are applicable to most IC""s, they are particularly a problem for FPGA""s.
More specifically, when it comes to re-programmable logic arrays such as Field Programmable Gate Arrays (FPGA""s), practitioners in the art of mass-production testing have begun to recognize that very large numbers of conductors of differing lengths, of differing orientations, and of other differing attributes may have to be each individually and methodically tested even as such conductors are connected to respective, but operationally-questionable, programmable signal routers (e.g., PIP""sxe2x80x94Programmable Interconnect Points) of various kinds. Practitioners want to be able to economically test each interconnect line for its ability to cleanly transmit a logic xe2x80x9c1xe2x80x9d level or pulse without interference from surrounding lines or routers, and counterposingly, to be able to economically and further test each interconnect line for its ability to cleanly transmit a logic xe2x80x9c0xe2x80x9d level or pulse, again without interference from surrounding lines or routers. This can be a massive undertaking in densely wired circuitry such as modern FPGA""s because their signal-routing switchboxes (e.g., PIP matrices) tend to be heavily populated and this leads to exponentially increasing numbers of possible interconnect permutations.
One approach that has been proposed for tackling this massive problem is called AND/OR tree testing. It is described in a research paper by W. K. Huang, F. J. Meyer, and F. Lombardi, entitled xe2x80x9cAn Approach for Detecting Multiple Faults in FPGAsxe2x80x9d, Dept. of Computer Science, Texas AandM University). Briefly, when AND/OR tree testing is carried out, selected ones of the programmable logic circuits of the FPGA are configured to each implement a four-input, receipt-verifying and result-forwarding circuit consisting of: (1) an AND gate, (2) an OR gate, and (3) a 2-to-1 dynamic multiplexer.
More specifically, under AND/OR tree testing, the progression of a respective logic xe2x80x9c1xe2x80x9d pulse can be timed and verified as it snakes its way from a first I/O pin, and through a logic-blocks implemented series of AND gates to a second I/O pin. If the logic xe2x80x9c1xe2x80x9d pulse (a 0-to-1-to-0 transition) is detected at the second I/O pin, that information can be used to verify that interconnect resources within the series chain of AND gates can propagate such a logic xe2x80x9c1xe2x80x9d pulse. Similarly, the progression of a respective logic xe2x80x9c0xe2x80x9d pulse can be timed and verified as it snakes its way from the same first I/O pin, and through a logic-blocks implemented series of OR gates to the second I/O pin. If the xe2x80x9c0xe2x80x9d pulse is seen to be faithfully reproduced a short time later at the second I/O pin, that information can be used to verify that interconnect resources within the series chain of OR gates can propagate such a xe2x80x9c0xe2x80x9d pulse.
The reason why the four-input, receipt-verifying and result-forwarding circuit is used in the AND/OR tree testing of W. K. Huang et. al is to avoid having to re-program the under-test FPGA in between the xe2x80x9c1xe2x80x9d pulse propagating test and the xe2x80x9c0xe2x80x9d pulse propagating test. Each re-programming of a given FPGA can consume as much as 500 mS (milliseconds) or more. It is the re-programming rather than the testing itself which tends to consume the bulk of overall test time. With Huang""s dynamically-switchable, receipt-verifying and result-forwarding circuit, one or the other of a combinatorial logic series of AND gates or OR gates may be established for timing and verifying respective propagation of a xe2x80x9c1xe2x80x9d pulse and a xe2x80x9c0xe2x80x9d pulse.
A main drawback of the AND/OR tree method is that a very large number of different FPGA configuration patterns may still have to be programmed into a same IC in order to verify that all, or a fair majority of its interconnect resources are working properly. As already explained, each re-programming of a new configuration pattern into the FPGA can consume as much as 500 mS (milliseconds) or more. If the number of different patterns needed for high-confidence verification is on the order of 500 or more, then a single, under-test IC may consume as much as 250 seconds (over 4 minutes) of testing time or more, simply for the pattern programming time. This magnitude of per-chip testing time is not acceptable. Note that we are not even counting the amount of additional time it may take to actually perform the interconnect verification tests, or other logic function tests. The pattern re-programming time is by itself a major problem.
For one specific family of high-density FPGA""s (60,000 gate devices), the present inventors calculated that approximately 800 pattern re-programmings would be required for each chip in order to thoroughly test just a partial subset of its interconnect resources under the AND/OR tree method. This is not acceptable. A radically different solution is needed.
In accordance with the invention, a plurality of feedback-wise self-sustaining and parallel-wise executing sequential state machines are programmably established in an under-test FPGA device and each is seeded with a respective starting state. The plural sequencers are preferably programmed to step through a plural number of unique, excitation states where that maximal number is dependent on the state-storing and state-recognizing capabilities of the programmable logic units that are used to implement the sequencers. The feedback of each sequencer is provided through a respective and under-test part of the FPGA""s interconnect structure. If the corresponding set of feedback-supporting, interconnect resources are operating correctly for each given sequencer, that sequencer should independently step from its starting state, and through a feedback-sustained sequence of plural, unique and interconnect-challenging, excitation states until reaching a predefined pause step. The latter pause step is also defined herein as an interconnect-verifying, readout state. There can be more than one interconnect-verifying, readout state in a full testing cycle, but the number of pause states should be smaller than the total number of unique, interconnect-challenging states.
At each interconnect-verifying, readout state, a serial readout may be conducted of a shadowing version of the state-holding registers. (The state-holding registers preferably retain their states during this readout.) If indeed, the corresponding set of feedback-supporting, interconnect resources of each sequencer was operating correctly, then the serially-read out state for that sequencer should be what was expected. On the other hand, if the corresponding set of feedback-supporting, interconnect resources of a given sequencer is defective; because of a short circuit and/or an open circuit and/or a stuck signal router; then the readout state for that sequencer will probably be other than what was expected.
It is possible however, that in a given peculiar set of circumstances, the readout state of a sequencer with defect-containing interconnect nonetheless turns out to be the same as the readout that was expected for that pause phase. The likelihood of the expected matching the actual readout again and again in subsequent pause-and-verify states is relatively small. As such, detection of expected readout states at multiple pause points should provide a high degree of confidence that the challenged interconnect resources within the sequencer are being fully exercised and demonstrated to be operating properly.
A first advantage of carrying out interconnect verification testing in accordance with the sequencer-based aspect of the invention is that such can be easily scaled to handle larger and larger sized FPGA""s. As the number of logic blocks in an FPGA family grows, one can simply implement more sequencers for parallel processing the interconnect-challenging test vectors. Test time may be kept roughly the same even though the number of logic blocks increases. (Serial readout time may increase, though.) Also, if the feedback loop in each sequencer is kept relatively short and fast, then scaling to larger-sized FPGA""s should not add significantly to overall test time because signal propagation delay through the series of challenged wires in each feedback loop remains roughly constant. This is to be contrasted with other approaches that use very long serial chains and therefore suffer from increasing delays as the size of the FPGA is scaled upwardly.
A second advantage of carrying out interconnect verification testing in accordance with the sequencer-based aspect of the invention is that such testing does not need to use a large number of pins at the package-to-exterior interface. Even a small pinout for just supporting JTAG or like boundary scan can be used. The test vectors may loop internally and in parallel. They do not have to be output in parallel from the device""s pinout. As a result, testing facilities do not need to keep on hand a large variety of different test programs, where each such program is custom tailored to a different kind of package type and/or a different member of an FPGA family. Also, specialized testing equipment with relatively high densities of probe fingers may not be needed because a rudimentary ability to interface with the chip""s boundary scan circuitry should be enough. Even test platforms with small numbers of probes may be used providing the test equipment has enough interface pins or probes to interface with the JTAG port of the under-test package or die. Thus, a wide variety of different kinds of test platforms may be used for carrying out interconnect verification testing in accordance with the sequencer-based and boundary scan aspects of the invention.
A third advantage of carrying out interconnect verification testing in accordance with the sequencer-based aspect of the invention is that the number of pattern reconfigurations made to the under-test FPGA can be greatly reduced. Thus the total time for pattern reconfigurations can be reduced. This can happen because each sequencer can be programmed to apply a large number of unique, interconnect-challenging test vectors for each pattern reconfiguration. Hence more tests may be performed per reconfiguration. Additionally, when a preferred, circuitous routing is used for each given feedback signal, where that circuitous routing sequences its interconnect-challenging signals through a large number of non-overlapping interconnect conductors and a correspondingly large number of routing switches, more of the interconnect resources can be simultaneously tested during each of the plural steps taken by each sequencer. This helps to reduce the number of pattern reconfigurations needed for thorough, or near-thorough interconnect verification testing.
Other aspects of the invention will become apparent from the below detailed description.